High-k metal gate (HKMG) technology for CMOS devices
High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves the dielectric constant. To help with fermi-level pinning and to allow the gate to be adjusted to low threshold voltages, a metal gate is used instead of a polysilicon gate. By combining the metal gate and low-k dielectric, HKMG technology reduces gate leakage, thereby increasing the transistor capacitance and allowing chips to function with reduced power needs.
The two common process flows to pattern the HKMG stack are gate-first and gate-last. The gate-first HKMG process is very sensitive, as the capping metal that must be patterned is very thin. Photoresists do not adhere well to the metal layers, which is made worse by the wet chemistries used to etch the capping metal.
Brewer Science® developer-soluble bottom anti-reflective coatings (DBARCs) are an enabling technology used to pattern the metal capping layers in the gate-first HKMG process. DBARCs protect the substrate by patterning with the photoresist and eliminating the use of reactive ion etching (RIE). Additional value is found in the crosslinking ability of a DBARC, which increases the substrate adhesion, allowing the wet-etch process to transfer the pattern through the capping metal.