As semiconductor devices evolve, smaller and smaller feature sizes are required to achieve the performance desired by the consumer. Smaller features give rise to lower power consumption for mobile devices, less expensive devices due to the ability to manufacture more chips per wafer, and faster overall speed.
Why multilayer?
Smaller feature sizes also lead to higher aspect ratios in the photoresist, which cause pattern collapse and result in smaller processing windows. Therefore, photoresists have become thinner to offer higher resolution and to overcome pattern collapse. Typical photoresist thicknesses for today’s cutting-edge immersion processing are in the range of 60 nm to 100 nm, whereas typical photoresist thicknesses just a few years ago were about 150 nm. The trade-off for using thinner photoresists is a smaller etch budget for pattern transfer into the substrate. For this reason, multilayer patterning is needed.
How multilayer patterning works
Current multilayer patterning uses a thin photoresist with a thin inorganic or organometallic etch barrier layer (a hardmask, HM) that is deposited by either chemical vapor deposition (CVD) or spin-coating processes over the top of a thicker layer that is high in carbon content (a carbon hardmask, CHM). Some examples of CVD hardmask layers include SiON, SiN, and TiN. Organosilicates are one example of a spin-on hardmask. An example of a carbon hardmask applied by CVD is alpha-carbon. Spin-on carbon (SOC) hardmask layers consist of organic polymer solutions that are high in carbon content by design.
High inorganic content in the hardmask layer is important for transferring the photoresist image through the multilayer stack. High inorganic content allows for faster plasma etching in a fluorinated etch gas, thus reducing the photoresist thickness required to pattern the hardmask. High inorganic content also slows the hardmask etch rate in oxygen plasma so that the hard mask maintains its integrity while transferring the photoresist pattern into the carbon hardmask layer.
High carbon content in the carbon hardmask layer is important because carbon etches slowly in the plasma gases typically used to etch into inorganic substrates such as silicon, polysilicon, SiO2, and low-k dielectrics.
Multilayer processing with spin-on coatings is a simpler process than CVD multilayer processing. The entire multilayer stack is applied in the coating module of a track, which eliminates the need to transfer wafers to another module for deposition.
OptiStack® multilayer systems
Brewer Science® OptiStack® systems simplify the overall lithography process by offering a universal lithography platform that eliminates topography dispersion and maintains optimal optical interfaces in the same focal plane, regardless of the substrate optical properties.
OptiStack® HM710 material on OptiStack® SOC110D material. High etch selectivity permits very thin hard mask and straight profiles.
View OptiStack® systems customer advantages
One of the most critical variables in spin-coating processes is coating uniformity. In many cases, engineers are challenged with achieving ultralow total thickness variation at high film thicknesses while conserving expensive materials. To achieve such a highly uniform coating, automated control of the solvent vapors is essential. A closed bowl environment combined with a programmable exhaust module allows the solvent vapor concentration to be precisely controlled at various stages in the spin-coating process.
Creating a solvent-rich environment: Prewet dispense step
Typically, creating a solvent-rich environment is optimal for the initial dynamic dispense. This step is often accomplished through a prewet dispense step that is performed immediately before thick-film deposition. The step consists of dispensing a small volume of solvent onto the substrate surface, which quickly casts the solvent onto the interior bowl surfaces. This preparation has the dual benefits of increasing vapor enrichment in the spin chamber and prepping the surface of the substrate for optimal spreading characteristics. The spin chamber exhaust is typically programmed to 0% flow during this phase, which mitigates the risk of solvent evaporation prior to the dispense step.
Applying the material: Dynamic dispense step
The next phase, the dynamic dispense step, uniformly spreads the coating material across the wafer surface. The material is applied while the substrate is spinning at relatively low speeds of 200 to 500 rpm. The dynamic method enables optimal coverage of the surface area while minimizing the overall volume of wasted material. In many cases, viscous materials for thick-film applications will be delivered through a positive displacement pump and will have maximum shot sizes of 16 to 20 ml of total volume. Following the deposition step, the spin speed is slowly ramped to establish the final thickness. The programmable exhaust control plays a significant role in determining the speed required for the desired thickness. Depending on the material composition, molecular weight, and viscosity, the exhaust is generally throttled at 0% to 50% closed. The combined effects of spin speed, vapor concentration, and time will determine the final coating thickness.
Stabilizing the film: Drying step
Typically, the casting process is followed with a longer drying step to remove residual solvents and increase the physical stability of the film. Thin-film applications often utilize a higher spin speed for this effect; however, many thick films must remain at the casting speed and/or slow to a lower speed to prevent additional thinning. We recommend the programmable exhaust be set at 100% during this phase to assist in faster solvent evaporation. This setting provides the additional benefit of removing the residual vapors from the chamber before the tool operator opens the lid at the conclusion of the process.
Spin speed, acceleration (centrifugal) force, and drying rate are the most important variables in determining the final film thickness and uniformity. Brewer Science® Cee® products provide these precision controls to enable optimal coating results for lab-scale and pilot-line applications.
Cee® 200CBX shown with optional programmable exhaust module.
One of our recent articles discussed the creation of through-silicon vias using ProTEK® PSB photosensitive etch protection material. In this post, we will follow up by addressing a few of the frequently asked questions regarding our etch protection materials.
What etchants can these materials withstand?
Three classes of Brewer Science® ProTEK® materials are available to provide protection against alkaline and acid etchants as well as Bosch deep reactive ion etching (DRIE) processes. ProTEK® B3 and ProTEK® PSB coatings are designed to protect against alkaline etchants. ProTEK® A3 and ProTEK® PSA materials are designed to protect against acid etchants. ProTEK® SR scratch-resistant coating resists the etch gases used in the Bosch DRIE process.
ALKALINE: ProTEK® B3 and ProTEK® PSB coatings withstand KOH, TMAH, NaOH, and NH4OH at elevated temperatures as well as some acids such as hydrochloric, sulfuric, and phosphoric acids and buffered oxide etchant (BOE) at room temperature.
ACID: BSI.P09047 and BSI.P09022 coatings are resistant to acid etchants such as nitric, liquid hydrofluoric, acetic, and hydrochloric acids as well as BOE and HNA (which is HF, HNO3, and acetic acid in a ratio of 1:2:3.2). While these materials are also resistant to alkaline solutions, they may lose adhesion to the wafer during alkaline etching.
OTHER: ProTEK® SR material is resistant to some acid etchants such as hydrochloric, sulfuric, and phosphoric acids and BOE at room temperature. It is also resistant to the fluorinated etch gases used in the Bosch DRIE process such as SF6 and C4F8.
Do these materials require a primer?
Whether or not a primer is required to use ProTEK® coatings depends on the process. Coatings used during a long alkaline etch must have a primer. Without a primer, the coatings would eventually peel off the substrate during etching. The other materials do not typically need a primer, but the need for a primer does depend on the specific application.
For applications in which a wafer is coated with an acid-resistant coating and a short alkaline etch is needed before the acid etch, a primer is not normally needed. The necessity for a primer will depend on how short the alkaline exposure is and how aggressive the etch is in terms of bath temperature and concentration.
A primer is required if BSI.P09022 coating will be used as an etch mask for liquid HF etching of glass. A single primer for this application has not yet been named, but customers have demonstrated success using a chrome-nickel or chrome-gold seed layer.
How thick must these films be to resist the wet etchant?
A thick film is not required for alkaline etch protection. As long as a continuous film is applied, an alkaline etch solution will not penetrate the coating. However, a thicker coating may be required when working with acids. The thickness will be determined by the etchant, the etchant concentration, and the etch time.
Visit our MEMS FAQs page for answers to other commonly asked questions.
Through-silicon vias (TSVs) are becoming increasingly common for high-speed and high-bandwidth connections on a chip. TSVs are especially important in 3D packaging schemes and are also used in many sensor, MEMS, and LED devices.
While it is common to use deep reactive ion etching (DRIE) for creating the TSVs, wet etching of the silicon to create vias is a cost-effective process. In contrast to DRIE’s single-wafer processing that uses more expensive plasma etching equipment, wet-etch TSV formation allows batch processing using relatively inexpensive equipment (wet processing baths).
Etch mask challenges
One of the main challenges in wet etching of silicon is availability of a cost-effective etch mask scheme for protection during etching.
Conventional schemes for etch masks include chemical-vapor-deposited (CVD) silicon nitride (SiN) or silicon dioxide–based etch masks. The mask process involves several steps including specialized tools for high temperature CVD processing and dry-etch processing apart from the use of standard photolithography tools. The masking process and required toolset effectively raise the cost of ownership (CoO) of a wet-etch process, which would otherwise be a cost-effective option for users.
Brewer Science presents an elegant spin-on etch mask solution that minimizes the number of steps used for creating an etch mask and avoids the use of CVD-based tools for etch mask creation. The etch mask offers complete protection without pin-holes or delamination during silicon etching using alkaline etch baths (potassium hydroxide [KOH] or tetramethyl ammonium hydroxide [TMAH]).
Figure 1. Comparison of etch mask process scheme for wet-etch protection using (a) silicon nitride mask and (b) ProTEK® PSB spin-coatable etch mask
Cost-effective TSV creation
We have created TSVs using ProTEK® PSB photosensitive material for etch protection. The process provides good control and etch pattern integrity that is suitable for commercial production of TSV wafers for advanced interconnect structures.
Figure 2. SEM images showing TSVs of various dimensions created using ProTEK® PSB coating as an etch mask
Brewer Science® ProTEK® materials can protect entire surfaces and serve as effective etch masks for creating TSVs and other microstructures on silicon using wet etching. ProTEK® products provide a low-CoO option compared to conventional CVD-based etch mask techniques. As wafers become thinner, wet-etch TSV formation becomes more viable, providing a low-cost option to device manufacturers.
Thin-wafer processing trends
Several spin-coating process applications require the ability to uniformly coat, develop, and/or rinse (clean) thinned and fragile substrates. Safely handling these fragile materials is paramount and requires specially designed spin chucks and thin-wafer handling techniques. The substrates are made of a wide array of materials, and some of the more popular ones include flexible polymer films (for example, fluorinated ethylene propylene [FEP] and polyester [PET]) and metal foils (titanium, aluminum, and steel). These materials are common for markets within the optics, thin-film transistor (TFT) display, and photovoltaic (PV) industries. Thicknesses of the substrates often range from 50 to 100 µm (0.001 to 0.004 inch) and are cut into various shapes (round, square, and rectangular).
Moreover, we are seeing a growing migration in the microelectronics industry toward through-silicon via (TSV) technology for 3-D wafer stacking. This technology requires significant reduction in substrate thickness and exponentially increases the complexity of handling for every subsequent processing step. The thinned substrate materials include silicon for advanced packaging as well as compound semiconductor (CS) materials including gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), and silicon carbide (SiC) for high-power radio-frequency (RF) devices and light-emitting diodes (LEDs). The CS and III-V materials are extremely brittle and far more sensitive to both mechanical and thermal shock. Film frames are commonly used to support silicon (Si) and CS materials. A device wafer can be mounted onto a film frame after backside processing but while it is still supported by its carrier, as in the Brewer Science® ZoneBOND™ process, or following separation (debonding) from the carrier, as in the thermal slide debonding process, for subsequent transport, cleaning, and packaging.
Issues with standard vacuum spin chucks
Process engineers often encounter a major hurdle with standard vacuum chucks that use a series of concentric circles and/or small-diameter perforated holes to supply vacuum through the spin chuck surface. These designs distribute the vacuum unevenly across the surface and cause dimples, deflection, and/or, in worst-case scenarios, cracking. Furthermore, all of these detrimental anomalies will lead to less-than-optimal film characteristics across the substrate. A film frame support structure will assist in handling these delicate films; however, any irregular chuck topography will detrimentally affect total thickness variation (TTV). Therefore, specialized spin chucks are recommended to safely contact thinned substrates without risk to delicate structures and subsequent film uniformity.
Alternative spin chuck designs
For thinned substrates (< 250 µm thick), we have developed a porous ceramic insert design that has a distinct advantage of completely supporting the backside of any given substrate dimension. The chuck distributes the vacuum equally through a porous surface and mitigates any potential deflection, eliminating detrimental effects to your substrate or coat quality. These chucks are design specific and available for a wide array of shapes and sizes.
The porous ceramic design can also be adapted for thinned substrates mounted to film frames. Mechanical clamps and a porous ceramic insert combine for spin processing thinned substrates (< 250 µm thick) that have been taped to frames. The ceramic insert ensures complete and uniform backside support, while it distributes the vacuum source across the taped surface. This design also utilizes vacuum O-rings and mechanical clamps for securing the outer film frame to the chuck assembly and maintaining positive lock.
Although these chucks enable safe handling of ultrathinned substrates, they are exponentially heavier and create significantly more inertia than standard round vacuum chucks. To achieve adequate acceleration rates, these chucks can only be used on spin coaters with high-horsepower drive systems. All Brewer Science® Cee® spin coaters feature the industry’s highest-horsepower servo-motor indirect drive system and will allow the direct transfer of standard spin processing conditions. This system delivers the unique capability of combining porous ceramic chuck technology, existing high acceleration rates, and multiple spin-speed steps to fully optimize your thin-wafer processing application.
Cost of ownership plays an important role in lithography process materials and methods decisions. Process simplifications brought about by layer-to-layer synergy drive significant cost of ownership advantages for multilayer lithography systems such as the Brewer Science® OptiStack® system. Savings in mask engineering and manufacture are the greatest cost difference. Optical proximity correction (OPC) algorithms need only be determined once for all layers, rather than individually for each layer, which results in fewer mask corrections. Advanced devices with smaller critical dimensions benefit most from this system in that there are more layers at smaller critical dimensions, requiring greater mask design and production costs.
For the purpose of providing a cost of ownership estimate, we compared a process using the OptiStack® system on eight layers to a typical dyed resist process. Note that the OptiStack® system process would use the same OPC algorithm on all layers. More layers utilizing the same system will result in greater savings. We assumed that 2500 wafers[1] would be printed from each mask; this is said to be a typical usage - ASIC masks may be imaged on as few as 500 wafers. Mask design and mask production are the significant cost components in any analysis of lithography process cost of ownership[2]. For a high-performance mask set with 90-nm design rules, individual binary chrome-on-glass masks can cost $100,000 to produce, and phase shift masks can cost as much as $124,000[3]. As a conservative estimate, the average mask cost was taken to be $70,000 because some layers can be printed using DUV tools and masks. Accounting for these and other costs, the OptiStack® system saves about $674 per wafer. The cost comparison is shown in Table I. “Other Optistack system costs” are caused by additional materials and processing.
Using this type of multilayer system is likely to bring even more benefits to the overall fab cost and efficiency. Other areas to be studied in future work are the impact of simplified inventory arising from the need for fewer custom materials by layer or device.
References
1. Harry J. Levinson, Principles of Lithography, The Society of Photo-Optical Instrumentation Engineers, 2005.
2. Vivek Bakshi, Ed., EUV Lithography, SPIE Press, Bellingham, WA, 2009.
3. B. Grenon and S. Hector, “Mask costs, a new look,” Proceedings of SPIE, vol. 6281, 2006, 62810H.
Limitations of Moore's Law
Ultimately, performance of computers and other electronic products will be limited by transistor size and density. Because the semiconductor industry has pushed to create ever-smaller features with photolithography, engineers have been able to shrink transistors far beyond original expectations to dramatically increase the density of transistors on a chip, thereby enabling the phenomenal leaps we have seen in the functionality and speed of electronics. However, the rate of performance improvements has become slower than originally predicted by Moore’s law because of the length of the connections between transistors and between individual semiconductor devices in components.
Increasing computing speed with through-silicon vias (TSVs)
Using through-silicon vias (TSVs) to directly interconnect semiconductor chips offers the promise of even greater functionality and faster computing speeds. Recent studies have indicated that computing speed may be increased by more than 10 times by using TSVs, and the associated decrease in inductive losses will reduce power consumption by more than 70%.
Implementation of TSV production requires the ability to handle and process ultrathin wafers as if they were at their full thickness. Most frequently, the full-thickness wafer is mounted on a rigid carrier using an adhesive that at later stages allows separation of the thin device wafer, which contains TSVs, from the carrier and removal of the adhesive. Although wafer-to-wafer bonding has been in use for some time for permanent bonding applications, and waxes have been used to bond wafers to carriers for thinning and subsequent removal, these processes have not been developed and optimized to allow further processing on the thinned wafer back side and permit separation from the carrier.
Supply chain options for 3D device packaging
Flexible options for temporary wafer bonding processes, with a variety of investment options, are available for 3DP applications. Device wafers can be mounted, demounted, and cleaned utilizing cost-effective equipment solutions. While mounted to carriers, device wafers may be thinned and may undergo backside processing as needed to create TSVs. Track-quality equipment performance enables scale testing of bonding, debonding, and cleaning processes. This flexibility, and the choice to select from a variety of options, creates a confidential pathway for completing thinned wafer processing feasibility work. Development time is reduced and the introduction of new 3DP applications to the market is accelerated.
For high-volume manufacturing (HVM) environments, Brewer Science has partnered with HVM equipment suppliers to qualify materials and processes for thin wafer handling needs. Customers can select an equipment supplier of their choice, one that can best meet their needs and provide the needed throughput and compatibility with their existing production environments. These suppliers offer equipment for mounting device wafers to carriers and then separating and cleaning the thinned wafers for final packaging.
Brewer Science technology provides customers flexibility for device development, process confirmation, and eventual scale to production.
With the explosion in demand for devices that include features in the tens to hundreds of microns, wet-etching is seeing new relevance. Light-emitting diodes (LED), microfluidic devices, ink-jet printer heads, sensors, and many other devices are being mass produced in semiconductor-fab-like environments. However, these feature sizes often do not demand the precision, of plasma etching, nor can they tolerate the cost.
One challenging reality of wet etching is that the entire wafer is exposed to the etchant. To advance the use of such cost-effective batch processing, etch protection schemes must be employed. Brewer Science’s ProTEK® materials are spin-applied polymeric coatings engineered to withstand commonly used etchants, enabling myriad protection strategies.
Blanket Etch Protection
Blanket protection refers to coverage of an entire wafer surface and can even include wafer edge protection. Blanket protection is also discussed in a previous blog article describing its use in deep reactive ion etching (DRIE).
Patterned Etch Protection
Sometimes blanket protection is not needed. It is often desirable to etch specific areas on a wafer surface while protecting others. Photosensitive protective materials, such as ProTEK® PSB coating, address this need. An increasingly common example occurs in the manufacture of high-brightness LEDs (HB LEDs). To improve light extraction, the surface of the light-emitting material is roughened using a harsh wet-etching process. However, other elements of the device (e.g., metal pads) would be damaged during the etch.
ProTEK® PSB coating can be pattern-exposed and developed to cover only these sensitive elements, and can be subsequently removed without damaging the device.
Conclusion
Processes utilizing the ProTEK® family of materials and processes enable surface etch protection, patterned etch protection, and edge protection. These materials can be used in combination to address a wide range of processing needs, providing lower-cost options to device manufacturers.
Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas). These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range. For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 µm deep and 50 µm in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them. This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.
Many methods exist to planarize substrates, but three are compatible with a standard lithography track: the dry-etch-back, wet-develop-back, and expose-and-develop methods.
Dry-etch-back method
The dry-etch-back method of planarizing is straightforward. Typically an organic film is coated on the wafer. This material must have self-leveling properties to minimize the difference in overburden between areas with high feature density and areas with low feature density.
Overburden is the thickness of material extending beyond the top of the trenches. Self-leveling is the tendency of the material to flow or re-flow during processing to create a uniform, flat surface across the wafer.
Once the material is coated and baked, the wafer is placed in a dry-etch chamber and oxygen ashed to remove the overburden.
The advantage to this method is that a wide range of materials can be used. Depending on the selection of the material, the methods for removing the fill include dry etching, wet etching (with solvent or developer), or thermal decomposition.
The disadvantage of this method is that it does require a dry-etching tool. Also, during the dry-etch-back process, other organic films on the substrate may be damaged.
Wet-develop method
The next method of planarizing a substrate is wet developing. This method is similar to the dry-etch-back process except that TMAH developer or a solvent is used to remove the overburden. For many of our materials, we find that the etch rate of the overburden material is much faster than the etch rate of the material in the vias or trenches. This difference reduces the iso-dense variance.
An advantage of this method is that all the processing can be performed on a standard litho track. Also, the film can be later removed by the same wet processing. The disadvantage is that the ability to be removed in developer or solvent may limit downstream processing. In some cases, the material can be cured after developing so that it is no longer soluble. This, however, then limits later removal to dry etching only.
Expose-and-develop method
In the expose-and-develop method, a photosensitive material with self-leveling properties is used. The material is coated on the wafer and then baked. The wafer is then exposed by photolithography (the material is typically negative acting) to set the material in the vias or trenches. The overburden in the open areas is removed by either a TMAH developer or a solvent developer, depending on the planarizing material being used. After exposure, the material in the vias is normally removed by plasma etching.
Brewer Science offers many materials that can be used to level the surface of the substrate. Selecting the correct material depends on the scale of the structures (nanometer, micrometer, or millimeter), the aspect ratios, and the desired processing method.
Process application engineers often encounter a variety of complex challenges related to deposition by spin coating, as many variables affect the quality of the spin-applied coating. These variables have critical effects on the overall coating uniformity, coating thickness, and subsequent device yield. Some of the more influential variables that must be controlled precisely are spin speed, acceleration, and airflow/fume exhaust.
Typical spin-coating recipes involve dispensing a small puddle of fluid resin onto the center of a round substrate. This material spreads due to the radial centripetal acceleration force and evenly flows across the entire surface of the substrate. Final coating thickness and coating uniformity (measured as total thickness variation) are affected by final rotational speed, acceleration, ambient airflow (turbulence), and fume exhaust. Process engineers have utilized spin-coating techniques for decades, and they produce predictable results when standard round substrates are used.
Standard round substrates feature an inherent advantage in airflow dynamics compared to other exterior shapes in that they generally feature smooth, contoured (radial) edges and cause minimal disruption to the ambient air environment. This shape produces relatively uniform evaporation rates, as the fluid moves toward the radial edge during the spreading and subsequent drying steps. The resulting edge profile effect is very consistent and can be optimized through many standard process techniques.
Not all substrates are round, however. Square and rectangular shapes are commonly processed for a wide array of applications, including semiconductor photomasks, displays, and photovoltaic (PV) solar panels. These square and rectangular substrates create unique and complicated challenges for spin-coating applications through increased air turbulence. The leading edge of a square or rectangle causes significant turbulence when it contacts the internal spin bowl atmosphere, which leads to uneven evaporation of the film resin and anomalies in both thickness and uniformity of the coated film. Common film imperfections seen on square or rectangular substrates are often referred to as “edge buildup,” “fringing,” or corner “interference bands.”
Using a recessed spin chuck elegantly solves these problems by virtually eliminating the air disruption and resulting film non-uniformity. This design emulates a round substrate and removes the effect of the leading edge of the square or rectangle, thus dissipating the normal turbulence in the spin bowl atmosphere. These chucks virtually eliminate edge interference bands (corner fringing) and are custom-designed for each specific substrate dimension. Additional advantages of this design are its ability to auto-center and to provide both lateral and vacuum grip, as well as its ability to protect the back surface of the substrate and mitigate potential contamination.
While recessed chucks have important advantages, one disadvantage is that they are magnitudes heavier and create considerably more inertia than that created by standard round substrates. This added weight has a negative impact on spin speed acceleration. Any reduction in spin speed acceleration toward the final spin velocity can have dramatic effects on the final properties of the coated film. Because the resin begins to dry during the initial part of the spin cycle, it is important to accurately and aggressively control acceleration rates. In many cases, up to 50% of the solvents in the resin will be lost to evaporation in the first few seconds. Many process engineers utilize “snap” spin recipe techniques to aggressively cast the material from the center to edge in less than 3 seconds with maximum acceleration (5,000-20,000 rpm/s), followed by a much slower (< 500 rpm) drying step.
Unfortunately, many standard spin coaters lack the necessary horsepower or torque in their spindle drives to directly transfer spin recipe parameters (speed and acceleration) from standard-diameter substrates to recessed chuck applications. The Brewer Science® Cee® line of spin coaters and developers feature indirect drive systems with the industry’s highest horsepower (servo motor) and will allow the direct transfer of standard spin process conditions, even when using the heavier recessed chucks. This feature enables the unique capability of combining recessed chuck technology with existing high acceleration rates and multiple spin speed steps to virtually eliminate edge effect issues that can arise with irregular substrates.